1. Field of the Invention
The present invention relates to a chemical mechanical polishing (CMP) process for fabricating a semiconductor device, and more particularly, to a CMP process for isolating a self-aligned contact pad.
2. Description of the Related Art
In recent years, as the integration density of semiconductor devices has increased, the line width and the interval between lines have been reduced. Thus, the resolution of a photolithographic process is being markedly increased. However, alignment techniques cannot keep up with the increased resolution. Therefore, it is very important to minimize the generation of misalignment in fabrication processes of semiconductor devices.
To secure the misalignment margin, a self-aligned contact (SAC) process is typically used as a method of forming a pad for electrically connecting upper and lower layers.
FIGS. 1 and 2 are cross-sectional views illustrating a method of forming conventional SAC pads.
Referring to FIG. 1, an isolation region 104 is formed using an active mask (not shown) in a semiconductor substrate 100 to define an active region 102. Next, a gate stack 110 is formed using a gate mask on the semiconductor substrate 100. The gate stack 110 is formed by sequentially stacking and patterning a gate insulating layer 111, a gate conductive layer 112, and a gate-capping layer 113. In some cases, to reduce gate resistance, a metal silicide layer may be formed between the gate conductive layer 112 and the gate-capping layer 113. Afterwards, gate spacers 120 are formed to cover sidewalls of the gate stack 110, and an insulating layer 130 is formed on the semiconductor substrate 100 between the gate spacers 120. The insulating layer 130 is formed of a silicon oxide layer, while the gate spacers 120 and the gate capping layer 113 are formed of a silicon nitride layer having an etch selectivity with respect to the silicon oxide layer.
After forming the gate spacers 120, a mask pattern 160 is formed so as to expose only a portion to be etched. Next, the insulating layer 130, exposed between the gate spacers 120, is etched using the mask pattern 160 as an etch mask. Thus, a contact hole 140 is formed so as to expose a portion of the surface of the semiconductor substrate 100 between the gate spacers 120. While the insulating layer 130 is removed using an etch process, the gate capping layer 113 and the gate spacers 120, which constitute the gate stack 110, are also partially removed. As a result, a step difference d occurs between the gate stack 110 covered with the mask pattern 160 and the gate stack 110 exposed during the etch process.
Referring to FIG. 2, after the etch process for forming the SAC hole is performed, the mask pattern (160 of FIG. 1) is also removed. Next, a conductive material layer (e.g., a polysilicon layer), which will be used as contact pads 150, is formed on the entire surface of the resultant structure. After that, a CMP process is performed to form the contact pads 150, which are isolated from each other by the gate stack 110 on the active region 102 of the semiconductor substrate 100. The contact pads 150 are used as buried contact (BC) pads or direct contact (DC) pads.
As described above, forming the SAC pads requires performing the etch process and the CMP process for forming SAC holes. Also, during the etch process for forming the SAC holes, the gate capping layer 113 is partially removed together with the insulating layer 130. Thus, the step difference d occurs between the adjacent gate stacks 110. The step difference d affects the process time of the subsequent CMP process. That is, the CMP process time required for sufficiently isolating the adjacent SAC pads 150 is varied according to the step difference d.
Conventionally, a CMP process is initially performed on a sample and then whether or not SAC pads are isolated from each other is checked using the sample. Afterwards, the CMP process is performed on a semiconductor substrate by adjusting a CMP process time based on the checked result. However, an etch process for forming SAC holes, which is required before performing the CMP process, may cause a change in the step difference d between the gate stacks 110, which is not considered in the conventional method. Therefore, in a case where the step difference d between the gate stacks 150 is changed by the etch process for forming the SAC holes, the CMP time cannot be appropriately set. As a result, the SAC pads may not be completely isolated from each other.